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| Si4313-B1 Si4313 L OW -C O S T I S M RECEIVER Features Frequency range = 240-960 MHz Sensitivity = -118 dBm Low power consumption Data rate = 0.2 to 128 kbps FSK, GFSK, and OOK modulation schemes Power supply = 1.8 to 3.6 V Ultra low power shutdown mode Digital RSSI Wake-up timer Auto Frequency Calibration (AFC) Clear channel assessment Programmable RX BW 2.6-620 kHz Preamble detector RX 64 byte FIFO -40 to +85 C temperature range Integrated voltage regulators Frequency hopping capability On-chip crystal tuning 20-pin QFN package Low BOM Single capacitor matching network Power-On-Reset (POR) Single-ended antenna configuration Ordering Information: See page 46. Pin Assignments Si4313 XOUT nSEL 15 SCLK 14 SDI 13 SDO 12 VDD_DIG 7 GPIO_0 8 GPIO_1 9 GPIO_2 10 11 NC VDR nIRQ SDN VDD 1 XIN Applications 20 19 18 17 16 Remote control Weather station Personal data logging Health monitors NC 2 NC 3 RX 4 NC 5 6 NC Description The Si4313 is a single-ended universal ISM receiver for cost-sensitive applications featuring technology developed for the EZRadioPRO(R) product family. The Si4313 offers a simple, single-ended radio implementation over the 240-960 MHz frequency range. A receive sensitivity of up to -118 dBm allows for the creation of communication links with an extended range. The Si4313 offers excellent receiver performance in cost-sensitive radio applications. The Si4313 provides designers with advanced features to enable low system power consumption by offloading a number of RF-related activities from the system MCU allowing for extended MCU sleep periods. Additional features, such as an automatic wake-up timer, 64-byte RX FIFO, and a preamble detection circuit, are available. The Si4313's digital receive architecture features an ADC and DSP based modem that performs the radio demodulation and filtering for increased performance. GND PAD Patents pending Rev. 0.5 2/10 Copyright (c) 2010 by Silicon Laboratories Si4313 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si4313-B1 Functional Block Diagram 2 Rev. 0.5 Si4313-B1 TABLE O F CONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1. Test Condition Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.2. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.3. Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.7. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.8. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. Data Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1. RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7. Rx Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2. Modem Settings for OOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 8.3. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 8.4. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.5. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.6. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.7. RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Rev. 0.5 3 Si4313-B1 9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 10. Application Notes and Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.1. Rx LNA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13. Pin Descriptions: Si4313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 15. Package Outline: Si4313-B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16. Landing Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 17. Top Marking: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17.1. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4 Rev. 0.5 Si4313-B1 LIST OF FIGURES Figure 1. Application Example................................................................................................... 16 Figure 2. SPI Timing.................................................................................................................. 18 Figure 3. SPI Timing - READ Mode ..........................................................................................19 Figure 4. SPI timing - Burst Write Mode.................................................................................... 19 Figure 5. SPI timing Burst Read Mode...................................................................................... 19 Figure 6. State Machine Diagram.............................................................................................. 20 Figure 7. Rx Timing ................................................................................................................... 23 Figure 8. Sensitivity at 1% PER vs. Carrier Frequency Offset ................................................. 24 Figure 9. FIFO Threshold .......................................................................................................... 30 Figure 10. POR Glitch Parameters............................................................................................ 34 Figure 11. WUT Interrupt and WUT Operation.......................................................................... 38 Figure 12. Low Duty Cycle Mode .............................................................................................. 39 Figure 13. RSSI Value vs. Input Power..................................................................................... 40 Figure 14. Reference Test Card................................................................................................ 41 Figure 15. RX LNA Matching Circuit ......................................................................................... 42 Figure 16. 20-Pin Quad Flat No-Lead (QFN) ............................................................................47 Figure 17. 20-Pin QFN Landing Pattern.................................................................................... 48 Figure 18. Si4313 Top Marking .................................................................................................50 Rev. 0.5 5 Si4313-B1 LIST OF TABLES Table 1. DC Characteristics ........................................................................................................7 Table 2. Synthesizer AC Electrical Characteristics .....................................................................8 Table 3. Receiver AC Electrical Characteristics..........................................................................9 Table 4. Auxiliary Block Specifications...................................................................................... 11 Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ).................................... 12 Table 6. GPIO Specifications (GPIO_0, GPIO_1 and GPIO_2) ............................................... 13 Table 7. Absolute Maximum Ratings ........................................................................................ 14 Table 8. Operating Modes ........................................................................................................17 Table 9. Serial Interface Timing Parameters ............................................................................18 Table 10. Operating Modes Response Time ............................................................................20 Table 11. PLL Synthesizer Block Diagram ............................................................................... 28 Table 12. Minimum Receiver Settling Time .............................................................................. 31 Table 13. GFSK Modem Settings ............................................................................................. 32 Table 14. OOK Modem Settings .............................................................................................. 33 Table 15. POR Parameters ...................................................................................................... 34 Table 16. System Clock Frequency Options ............................................................................35 Table 17. LBD ADC Range ...................................................................................................... 37 Table 18. RX LNA Matching Values ......................................................................................... 42 Table 19. Register Descriptions ............................................................................................... 43 Table 20. Package Dimensions ................................................................................................ 47 Table 21. PCB Land Pattern Dimensions ................................................................................. 49 6 Rev. 0.5 Si4313-B1 1. Electrical Specifications Table 1. DC Characteristics1 Parameter Supply Voltage Range Symbol VDD RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF2 Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator, and RC Oscillator OFF RC Oscillator and Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator OFF Main Digital Regulator and Low Battery Detector ON, Crystal Oscillator and all other blocks OFF2 Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF2 Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled Synthesizer and regulators enabled Conditions Min 1.8 Typ 3.0 Max 3.6 Units V ISHUTDOWN -- 15 50 nA ISTANDBY -- 450 800 nA Power Saving Modes ISLEEP -- 1 -- A ISENSOR-LBD ISENSOR-TS IREADY Tune Mode Current RX Mode Current ITUNE IRX -- -- -- -- -- 1 1 800 8.5 18.5 -- -- -- -- -- A A A mA mA Notes: 1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in "1.1.1. Production Test Conditions" on page 14. 2. Guaranteed by qualification. Qualification test conditions are listed in "1.1.1. Production Test Conditions" on page 14. Rev. 0.5 7 Si4313-B1 Table 2. Synthesizer AC Electrical Characteristics1 Parameter Synthesizer Frequency Range Synthesizer Frequency Resolution2 Reference Frequency Input Level2 Synthesizer Settling Time2 Symbol FSYNTH-LB FSYNTH-HB FRES-LB FRES-HB fREF_LV Conditions Low Band High Band Low Band High Band When using external reference signal driving XOUT pin, instead of using crystal. Measured peak-to-peak (VPP) Measured from leaving Ready mode with XOSC running to any frequency including VCO Calibration Min 240 480 -- -- 0.7 Typ -- -- 156.25 312.5 -- Max 480 960 -- -- 1.6 Units MHz MHz Hz Hz V tLOCK -- 200 -- s Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in "1.1.1. Production Test Conditions" on page 14. 2. Guaranteed by qualification. Qualification test conditions are listed in "1.1.1. Production Test Conditions" on page 14. 8 Rev. 0.5 Si4313-B1 Table 3. Receiver AC Electrical Characteristics1 Parameter Synthesizer Frequency Range Symbol FRX (BER < 0.1%) (2 kbps, GFSK, BT = 0.5, f = 5 kHz)2 (BER < 0.1%) (40 kbps, GFSK, BT = 0.5, f = 20 kHz)2 (BER < 0.1%) (100 kbps, GFSK, BT = 0.5, f = 50 kHz)2 (BER < 0.1%) (125 kbps, GFSK, BT = 0.5, f = 62.5 kHz)1 (BER < 0.1%) (4.8 kbps, 350 kHz BW, OOK)2 PRX_OOK (BER < 0.1%) (40 kbps, 400 kHz BW, OOK)1 Conditions Min 240 Typ -- Max 960 Units MHz PRX_2 -- -118 -- dBm PRX_40 -- -105 -- dBm RX Sensitivity PRX_100 -- -101 -- dBm PRX_125 -- -98 -- dBm -- -- 2.6 -- -107 -99 -- 0.5 -31 -35 -40 -52 -56 -63 -30 -- -- -- 620 -- -- -- -- -- -- -- -- -54 dBm dBm kHz dB dB dB dB dB dB dB dB dBm RX Bandwidth2 RSSI Resolution 1-Ch Offset Selectivity2 2-Ch Offset Selectivity2 3-Ch Offset Selectivity2 Blocking at 1 MHz offset2 Blocking at 4 MHz offset 2 Blocking at 8 MHz offset 2 Image Rejection2 Spurious Emissions2 BW RESRSSI C/I1-CH C/I2-CH C/I3-CH 1MBLOCK 4MBLOCK 8MBLOCK ImREJ POB_RX1 Desired Ref Signal 3 dB above sensitivity, BER <0.1%. Interferer and desired modulated with 40 kbps F = 20 kHz GFSK with BT = 0.5, channel spacing = 150 kHz Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps F = 20 kHz GFSK with BT = 0.5 IF = 937 kHz -- -- -- -- -- -- -- -- Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in "1.1.1. Production Test Conditions" on page 14. 2. Guaranteed by qualification. Qualification test conditions are listed in "1.1.1. Production Test Conditions" on page 14. Rev. 0.5 9 Si4313-B1 Table 4. Auxiliary Block Specifications1 Parameter Low Battery Detector Resolution2 Low Battery Detector Conversion Time2 Microcontroller Clock Output Frequency 30 MHz XTAL Start-Up time 30 MHz XTAL Cap Resolution2 32 kHz XTAL Start-Up Time2 32 kHz XTAL Accuracy2 32 kHz RC OSC Accuracy2 POR Reset Time Software Reset Time2 Symbol LBDRES LBDCT Configurable to 30 MHz, 15 MHz, 10 MHz, 4 MHz, 3 MHz, 2 MHz, 1 MHz, or 32.768 kHz Conditions Min -- -- Typ 50 250 Max -- -- Units mV s FMC 32.768 k -- 30 M Hz t30M 30MRES t32k 32KRES 32KRCRES tPOR tsoft Using 20 ppm 32 kHz Crystal. -- -- -- -- -- -- -- 600 97 6 100 2500 16 100 -- -- -- -- -- -- -- s fF sec ppm ppm ms s Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in "1.1.1. Production Test Conditions" on page 14. 2. Guaranteed by qualification. Qualification test conditions are listed in "1.1.1. Production Test Conditions" on page 14. 10 Rev. 0.5 Si4313-B1 Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ)1 Parameter Rise Time2 Fall Time2 Input Capacitance2 Logic High Level Input Voltage2 Logic Low Level Input Voltage2 Input Current2 Logic High Level Output Voltage2 Logic Low Level Output Voltage2 Symbol TRISE TFALL CIN VIH VIL IIN VOH VOL 0 Rev. 0.5 11 Si4313-B1 Table 6. GPIO Specifications (GPIO_0, GPIO_1 and GPIO_2) Parameter Rise Time2 Fall Time2 Input Capacitance2 Logic High Level Input Voltage2 Logic Low Level Input Voltage2 Input Current2 Input Current if pull-up activated2 Symbol TRISE TFALL CIN VIH VIL IIN IINP IOMAXLL Maximum Output Current2 IOMAXLH IOMAXHL IOMAXHH Logic High Level Output Voltage2 Logic Low Level Output Voltage2 VOH VOL 0 Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. Qualification test conditions are listed in "1.1.1. Production Test Conditions" on page 14. 12 Rev. 0.5 Si4313-B1 Table 7. Absolute Maximum Ratings Parameter VDD to GND Voltage on Digital Control Inputs Voltage on Analog Inputs RX Input Power Operating Ambient Temperature TA Thermal Impedance JA Junction Temperature TJ Storage Temperature Range TSTG Value -0.3, +3.6 -0.3, VDD +0.3 -0.3, VDD +0.3 +10 -40 to +85 30 +125 -55 to +125 Unit V V V dBm C C/W C C *Note: Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This is an ESD-sensitive device. Rev. 0.5 13 Si4313-B1 1.1. Test Condition Definitions 1.1.1. Production Test Conditions TA = +25 C VDD = +3.3 VDC Sensitivity measured at 919 MHz. External reference signal (XOUT) = 1.0 VPP at 30 MHz, centered around 0.8 VDC. Production test schematic (unless noted otherwise). All RF input levels refer to the pins of the Si4313 (not the RF module). 1.1.2. Qualification Test Conditions TA = -40 to +85 C. VDD = +1.8 to +3.6 VDC. Based upon standard reference design test cards. All RF input levels refer to the pins of the Si4313 (not the RF module). 14 Rev. 0.5 Si4313-B1 2. Functional Description The Si4313 is an ISM wireless single-ended receiver with continuous frequency coverage over the entire 240-960 MHz band. The wide operating voltage range of 1.8-3.6 V and low current consumption make the Si4313 an ideal solution for low-cost, battery-powered applications. The Si4313 receiver uses a low IF architecture with a digital modem that performs the signal demodulation. The demodulated signal is output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO. A local oscillator (LO) is generated by an integrated VCO and Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates, output frequency, frequency deviation, and Gaussian filtering at any frequency between 240-960 MHz. The Si4313 is designed to work with a microcontroller, crystal, and a few passives to create a very low-cost system. Voltage regulators are integrated on-chip, which allows for a wide range of operating supply voltage conditions from +1.8 to +3.6 V. A standard 4-pin SPI bus is used to communicate with the microcontroller. Three configurable general-purpose I/Os are also available. Minimal antenna matching is required allowing the use of a single ac coupling capacitor which simplifies the system design and lowers the solution cost. 2.1. Application Example supply voltage C3 100 pF C4 100 nF C5 1 uF XOUT nSEL nIRQ SDN XIN X1 30 M H z VDD GP1 GP2 20 19 18 17 VDD NC 150 pF NC RX C1 NC 16 1 2 3 4 5 15 14 S C LK SDI SDO GP3 GP4 GP5 m icrocontroller S i4313 6 7 8 9 GPIO2 13 GPIO0 GPIO1 VDR C6 1 uF NC 10 V D D _D 12 11 N C VSS Figure 1. Application Example Rev. 0.5 15 Si4313-B1 2.2. Operating Modes The Si4313 provides several operating modes, which can be used to optimize the power consumption of the receive application. Depending upon the system communication protocol, an optimal trade-off between radio wake time and power consumption can be achieved. In general, any given operating mode may be classified as an Active mode or a Power Saving mode. Table 8 indicates which blocks are enabled (active) in each corresponding mode. With the exception of the Shutdown mode, all can be dynamically selected by sending the appropriate commands over the SPI. An "X" in any table cell means that the block can be independently programmed to be either ON or OFF (in that given operating mode) without noticeably impacting current consumption. The SPI block includes the SPI interface hardware and the register space. The 32 kHz OSC circuit block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal oscillator and wake-up timer. AUX (Auxiliary Blocks) includes the temperature sensor and low-battery detector. Table 8. Operating Modes Circuit Blocks Mode Name Digital LDC OFF Shutdown register contents lost OFF OFF OFF OFF OFF OFF 15 nA SPI 32 kHz OSC AUX 30 MHz XTAL PLL RX IVDD Standby Sleep Sensor Ready Tuning Receive register contents retained ON OFF ON ON ON ON ON OFF ON X X X X OFF X ON X X X OFF OFF OFF ON ON ON OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF ON 450 nA 1 A 1 A 800 A 8.5 mA 18.5 mA 16 Rev. 0.5 Si4313-B1 3. Controller Interface 3.1. Serial Peripheral Interface The Si4313 communicates with the host MCU over a standard three-wire SPI interface: SCLK, SDI, and nSEL. The host MCU can read data from the device on the SDO output pin. An SPI transaction is a 16-bit sequence which consists of a Read-Write (R/W) select bit followed by a 7-bit address field (ADDR) and an 8-bit data field (DATA). The 7-bit address field supports reading from or writing to one of the 128 8-bit control registers. The R/W select bit determines whether the SPI transaction is a read or write transaction. If R/W = 1, it signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the Si4313 every eight clock cycles. Timing parameters are shown in Table 9. The SCLK rate is flexible with a maximum rate of 10 MHz. Address MSB Data LSB SDI SCLK nSEL RW A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 xx xx RW A7 Figure 2. SPI Timing Table 9. Serial Interface Timing Parameters Symbol tCH tCL tDS tDH tDD tEN tDE tSS tSH tSW Parameter Clock high time Clock low time Data setup time Data hold time Output data delay time Output enable time Output disable time Select setup time Select hold time Select high period Min (nsec) 40 40 20 20 20 20 50 20 50 80 nSEL SDI SDO tEN tSW SCLK tSS tCL tCH tDS tDH tDD tSH tDE Diagram To read back data from the Si4313, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored on the SDI pin when R/W = 0. The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin. The READ function is shown in Figure 3. After the READ function is completed, the SDO pin will remain at either a logic 1 or logic 0 state depending on the last data bit clocked out (D0). When nSEL goes high, the SDO output pin will be pulled high by internal pull-up. Rev. 0.5 17 Si4313-B1 First Bit SDI SCLK RW =0 Last Bit D7 =X D6 =X D5 =X D4 =X D3 =X D2 =X D1 =X D0 =X A6 A5 A4 A3 A2 A1 A0 First Bit SDO D7 D6 D5 D4 D3 Last Bit D2 D1 D0 nSEL Figure 3. SPI Timing--READ Mode The SPI interface contains a burst read/write mode, which allows for reading/writing sequential registers without having to resend the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address. An example burst write transaction is shown in Figure 4, and a burst read is shown in Figure 5. As long as nSEL is held low, input data will be latched into the Si4313 every eight SCLK cycles. First Bit SDI SCLK nSEL RW =1 Last Bit D7 =X D6 =X D5 =X D4 =X D3 =X D2 =X D1 =X D0 =X D7 =X D6 =X D5 =X D4 =X D3 =X D2 =X D1 =X D0 =X A6 A5 A4 A3 A2 A1 A0 Figure 4. SPI timing--Burst Write Mode First Bit SDI SCLK RW =0 Last Bit A6 A5 A4 A3 A2 A1 A0 D7 =X D6 =X D5 =X D4 =X D3 =X D2 =X D1 =X D0 =X First Bit SDO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 nSEL Figure 5. SPI timing--Burst Read Mode 18 Rev. 0.5 Si4313-B1 3.2. Operating Mode Control There are three primary states in the Si4313 radio state machine: SHUTDOWN, IDLE, and RECEIVE. The SHUTDOWN state is designed to completely shut down the radio to minimize current consumption. There are five different configurations/options for the IDLE state that can be selected to optimize the Si4313 for the application requirements. "Register 07h. Operating Mode and Function Control 1" controls which operating mode/state is selected. The RX state may be reached automatically from any of the IDLE states by setting the rxon bit in "Register 07h. Operating Mode and Function Control 1". Table 10 shows each of the operating modes with the time required to reach RX mode as well as the current consumption of each mode. The Si4313 includes a low-power digital regulated supply (LPLDO), which is internally connected in parallel to the output of the main digital regulator (and is available externally at the VR_DIG pin); this common digital supply voltage is connected to all digital circuit blocks, including the digital modem, crystal oscillator, SPI, and register space. The LPLDO has extremely low quiescent current consumption but limited current supply capability; it is used only in the IDLE-STANDBY and IDLE-SLEEP modes. SHUTDOWN IDLE* RX *Five different options for IDLE Figure 6. State Machine Diagram Table 10. Operating Modes Response Time State Mode Shut Down State Idle States Standby Mode Sleep Mode Sensor Mode Ready Mode Tune Mode RX State 800 s 800 s 800 s 200 s 200 s N/A 450 nA 1 A 1 A 800 A 8.5 mA 18.5 mA Response Time to RX 16.8 ms Current in State/Mode (A) 15 nA Rev. 0.5 19 Si4313-B1 3.2.1. SHUTDOWN State The SHUTDOWN state is the lowest current consumption state of the device with nominally less than 15 nA of current consumption. The shutdown state may be entered by driving the SDN pin (Pin 20) high. The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access. When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN. 3.2.2. IDLE State There are fivefour different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and Function Control 1". All modes have a tradeoff between current consumption and response time to TX/RX mode. This tradeoff is shown in Table 10. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will default to the IDLE-READY mode. After a POR event the interrupt registers must be read to properly enter the SLEEP, SENSOR, or STANDBY mode and to control the 32 kHz clock correctly. 3.2.2.1. STANDBY Mode STANDBY mode has the lowest current consumption of the five IDLE states with only the LPLDO enabled to maintain the register values. In this mode the registers can be accessed in both read and write mode. The STANDBY mode can be entered by writing 0h to "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Additionally, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.2. SLEEP Mode In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately wake-up the radio at specified intervals. See "8.4. Wake-Up Timer and 32 kHz Clock Source" on page 36 for more information on the Wake-Up-Timer. SLEEP mode is entered by setting enwt = 1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.3. SENSOR Mode In SENSOR mode the Low Battery Detector may be enabled in addition to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in "Register 07h. Operating Mode and Function Control 1". See "8.3. Low Battery Detector" on page 34 for more information on this feature. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. 3.2.2.4. READY Mode READY Mode is designed to give a fast transition time to TXRX mode with reasonable current consumption. In this mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode by eliminating the crystal start-up time. READY mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function Control 1". To achieve the lowest current consumption state the crystal oscillator buffer should be disabled in "Register 62h. Crystal Oscillator Control and Test." To exit READY mode, bufovr (bit 1) of this register must be set back to 0. 3.2.2.5. TUNE Mode In TUNE mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give the fastest response to TXRX mode as the PLL will remain locked but it results in the highest current consumption. This mode of operation is designed for frequency hopping spread spectrum systems (FHSS). TUNE mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1". It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator. 20 Rev. 0.5 Si4313-B1 3.2.3. RX State The RX state may be entered from any of the Idle modes when the rxon bit is set to 1 in 'Register 07h. Operating Mode and Function Control 1'. A built-in sequencer takes care of all the actions required to transition from one of the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit: 1. Enable the main digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by internal timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is "0", default value is "1"). 5. Wait until PLL settles to required receive frequency (controlled by internal timer). 6. Enable receive circuits: LNA, mixers, and ADC. 7. Calibrate ADC (RC calibration). 8. Enable receive mode in the digital modem. Depending on the configuration of the radio all or some of the following functions will be performed automatically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional) including sync word, header check, and CRC. 3.2.4. Device Status Add 02 R/W R Func/Description Device Status D7 ffovfl D6 ffunfl D5 D4 D3 D2 D1 cps[1] D0 cps[2] POR Def -- rxffem headerr freqerr The operational status of the Si4313 can be read from the Device Status register, 'Register 02h' 3.3. Interrupts The Si4313 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h-04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h-06h). All enabled interrupt bits will be cleared when the microcontroller reads the interrupt status register. If the interrupt is not enabled when the event then it will not trigger the nIRQ pin, but the status may still be read at anytime in the Interrupt Status registers. Add R/W Func/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def -- -- 00h 01h 03 04 05 06 R R Interrupt Status 1 Interrupt Status 2 ifferr iswdet enfferr Reserved ipreaval Reserved Reserved ipreainval Reserved irxffafull irssi iext iwut Reserved ilbd ipkvalid ichiprdy icrcerror ipor R/W Interrupt Enable 1 enrxffafull enext Reserved enpkvalid encrcerror enrssi enwut enlbd enchiprdy enpor R/W Interrupt Enable 1 enswdet enpreaval enpreainval Rev. 0.5 21 Si4313-B1 3.4. System Timing Figure 7. RX Timing The VCO will automatically calibrate at every frequency change or power-up. The PLL T0 time is to allow for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 s. The total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 s. In certain applications, the PLL T0 time and the PLL CAL may be skipped for faster turnaround time. Contact applications support if faster turnaround time is desired. 3.5. Frequency Control To calculate the necessary frequency register settings, use the Silicon Labs' Wireless Design Suite (WDS) or Excel Calculator available from the product web page. These methods offer a simple, quick interface to determine the correct settings based on the application requirement. Add R/W Function/Description D7 D6 D5 D4 Data D3 D2 D1 D0 POR Default 75 76 77 R/W R/W R/W Frequency Band Select Nominal Carrier Frequency 1 Nominal Carrier Frequency 0 fc[15] fc[7] sbsel fc[14] fc[6] hbsel fc[13] fc[5] fb[4] fc[12] fc[4] fb[3] fc[11] fc[3] fb[2] fc[10] fc[2] fb[1] fc[9] fc[1] fb[0] fc[8] fc[0] 35h BBh 80h 3.5.1. Automatic State Transition for Frequency Change If registers 79h or 7Ah are changed in RX mode, the state machine will automatically transition the chip back to tune and change the frequency. This feature is useful to reduce the number of SPI commands required in a Frequency Hopping System. In turn, this reduces microcontroller activity, thereby reducing current consumption. 3.5.2. Frequency Offset Adjustment When the AFC is disabled, the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment and the AFC are both implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register; so, in order to get a negative offset, it is necessary to take the twos 22 Rev. 0.5 Si4313-B1 complement of the positive offset number. The offset can be calculated with the following formula: Desired Offset = 156.25 Hz hbsel + 1 fo 9:0 Desired Offset fo 9:0 = --------------------------------------------------------------156.25 Hz hbsel + 1 The adjustment range is 160 kHz in high band and 80 kHz in low band. For example, to compute an offset of +50 kHz in high band mode, fo[9:0] should be set to 0A0h. For an offset of -50 kHz in high band mode, the fo[9:0] register should be set to 360h. Add 73 74 R/W R/W R/W Func/Description Frequency Offset Frequency Offset D7 fo[7] Rsvd D6 fo[6] Rsvd D5 fo[5] Rsvd D4 fo[4] Rsvd D3 fo[3] Rsvd D2 fo[2] Rsvd D1 fo[1] fo[9] D0 fo[0] fo[8] POR Def 00h 00h 3.5.3. Auto Frequency Control (AFC) All AFC settings can be easily obtained from the excel settings calculator or by using the WDS Chip Configurator All AFC settings can be easily obtained from the settings calculator. This is the recommended method to program all AFC settings. This section is intended to describe the operation of the AFC in more detail to help understand the trade-offs of using AFC.The receiver supports automatic frequency control (AFC) to compensate for frequency differences between the transmitter and receiver reference frequencies. These differences can be caused by the absolute accuracy and temperature dependencies of the reference crystals. Due to frequency offset compensation in the modem, the receiver is tolerant to frequency offsets up to 0.25 times the IF bandwidth when the AFC is disabled. When the AFC is enabled, the received signal will be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a wider range of frequency offsets up to 0.35 times the IF bandwidth. The trade-off of receiver sensitivity (at 1% PER) versus carrier offset and the impact of AFC are illustrated in Figure 8. Figure 8. Sensitivity at 1% PER vs. Carrier Frequency Offset When AFC is enabled, the preamble length needs to be long enough to settle the AFC. In general, one byte of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened from 40 bits to 32 bits. Note that with the AFC disabled, the preamble length must still be long enough to settle the receiver and to detect the preamble (see "6.2. Preamble Length" on page 30). The AFC corrects the detected frequency offset by changing the frequency of the Fractional-N PLL. When the preamble is detected, the AFC will freeze for the remainder of the packet. In multi-packet mode the AFC is reset at the end of every packet and will re-acquire the frequency offset for the next packet. The AFC loop includes a bandwidth limiting mechanism improving the Rev. 0.5 23 Si4313-B1 rejection of out of band signals. When the AFC loop is enabled, its pull-in-range is determined by the bandwidth limiter value (AFCLimiter) which is located in register 2Ah. AFC_pull_in_range = AFCLimiter[7:0] x (hbsel+1) x 625 Hz The AFC Limiter register is an unsigned register and its value can be obtained from the EZRadioPRO Register Calculator spreadsheet. The amount of error correction feedback to the Fractional-N PLL before the preamble is detected is controlled from afcgearh[2:0]. The default value 000 relates to a feedback of 100% from the measured frequency error and is advised for most applications. Every bit added will half the feedback but will require a longer preamble to settle. The AFC operates as follows. The frequency error of the incoming signal is measured over a period of two bit times, after which it corrects the local oscillator via the Fractional-N PLL. After this correction, some time is allowed to settle the Fractional-N PLL to the new frequency before the next frequency error is measured. The duration of the AFC cycle before the preamble is detected can be programmed with shwait[2:0]. It is advised to use the default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling). If shwait[2:0] is programmed to 3'b000, there is no AFC correction output. It is advised to use the default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling). The AFC correction value may be read from register 2Bh. The value read can be converted to kHz with the following formula: AFC Correction = 156.25Hz x (hbsel +1) x afc_corr[7: 0] Frequency Correction RX AFC disabled AFC enabled Freq Offset Register AFC TX Freq Offset Register Freq Offset Register 24 Rev. 0.5 Si4313-B1 4. Modulation Options All modulation options are programmed in "Register 71h. Modulation Mode Control 2." 4.1. Modulation Type The Si4313 can be configured to support three alternative modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). The type of modulation is selected with the modtyp[1:0] bits in "Register 71h. Modulation Mode Control 2". modtyp[1:0] 00 01 10 11 Modulation Source Reserved OOK FSK GFSK 4.2. FIFO Mode In FIFO mode, the integrated FIFO is used to receive the data. The FIFO is accessed via "Register 7Fh. FIFO Access" with burst read capability. The FIFO may be configured specific to the application packet size, etc. (see "6. Data Handling" on page 29 for further information). When in FIFO mode, the chip will automatically exit the RX State when the ipkvalid interrupt occurs. The chip will return to the IDLE mode state programmed in "Register 07h. Operating Mode and Function Control 1". In RX mode, the rxon bit will only be cleared if ipkvalid occurs and the rxmpk bit (Address 08h bit [4]) is 0. When the rxmpk bit is set to 1, the part will remain in RX mode after successfully receiving a packet. A CRC, Header, or Sync error will generate an interrupt, and the microcontroller will need to decide on the next action. In RX mode, the preamble detection threshold and sync needs to be programmed so that the modem knows when to start filling data into the FIFO. When the FIFO is being used, the data being loaded into or out of the FIFO can still be observed by configuring the GPIO, which can be useful during development. 4.3. Direct Mode In many system implementations, it may not be desirable to use a FIFO, and, for this scenario, a "Direct Mode", which bypasses the FIFOs entirely, is provided. In Direct Mode, the RX data and RX clock are programmed directly to the GPIO and used by the microcontroller to process the data without using the FIFO. In direct mode, the preamble detection threshold (Reg 35h) still needs to be programmed. Once the preamble is detected, algorithms internal to the modem change. It is not required that the sync be programmed when direct mode is used for RX. 4.3.1. Direct Mode using SPI or nIRQ Pins In certain applications, it may be desirable to minimize the connections to the microcontroller or to preserve the GPIOs for other uses. For these cases, it is possible to use the SPI pins and nIRQ as the modulation clock and data. The SDO pin can be configured to be the data clock by programming trclk = 10. If the nSEL pin is LOW, then the function of the pin will be SPI data output. If the pin is high and trclk is 10, then, during the RX mode, the data clock will be available on the SDO pin. If trclk[1:0] is set to 11 and no interrupts are enabled in registers 05 or 06h, the nIRQ pin can also be used as the RX data clock. The SDI pin can be configured to be the data source for RX if dtmod = 01. Similarly, if nSEL is LOW, the pin will function as SPI data-in; if nSEL is HIGH, it will be the received demodulated data. Rev. 0.5 25 Si4313-B1 5. Internal Functional Blocks This section provides an overview of some of the key blocks of the internal radio architecture. 5.1. RX LNA The input frequency range for the LNA is 240-960 MHz. The LNA provides gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of gain control that is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the gain of the LNA and PGA so the receiver can handle signal levels from sensitivity to +5 dBm with optimal performance. 5.2. RX I-Q Mixer The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer consists of two double-balanced mixers whose RF inputs are driven in parallel. Local oscillator (LO) inputs are driven in quadrature, and separate I and Q Intermediate Frequency (IF) outputs drive the programmable gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL synthesizer operating between 240 and 960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO output. 5.3. Programmable Gain Amplifier The Programmable Gain Amplifier (PGA) provides the necessary gain to boost the signal level into the dynamic range of the ADC. The PGA must also have enough gain switching to allow for large input signals to ensure a linear RSSI range up to -20 dBm. The PGA has steps of 3 dB that are controlled by the AGC algorithm in the digital modem. 5.4. ADC The amplified IQ IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low current consumption and high dynamic range. The band-pass response of the ADC provides exceptional rejection of out of band blockers. 5.5. Digital Modem Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain, resulting in reduced area while increasing flexibility. The digital modem performs the following functions: Channel selection filter TX modulation RX demodulation AGC Preamble detector Invalid preamble detector Radio signal strength indicator (RSSI) Automatic frequency compensation (AFC) Packet handling including EZMAC(R) features Cyclic redundancy check (CRC) The digital channel filter and demodulator are optimized for ultra low power consumption and are highly configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured to support bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported ranging from 0.123 up to 256 kbps. The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. The configurable preamble detector is used to improve the reliability of the sync-word detection. The sync-word detector is only enabled when a valid preamble is detected, significantly reducing the probability of false detection. The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned 26 Rev. 0.5 Si4313-B1 channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power measurements for clear channel assessment (CCA), and carrier sense (CS), and listen before talk (LBT) functionality. Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital automatic frequency control (AFC) in receive mode. A comprehensive programmable packet handler including key features of Silicon Labs' EZMAC is integrated to create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast, group, and point-to-point communication. A wireless communication channel can be corrupted by noise and interference, and it is therefore important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller. The digital modem includes the TX modulator which converts the TX data bits into the corresponding stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to support GFSK, considerably reducing the energy in the adjacent channels. The default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may not be adjusted to other values. ntly reduce the load on the system microcontroller allowing for the use of a simpler and cheaper microcontroller. 5.6. Synthesizer An integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating from 240-960 MHz is provided on-chip. Using a synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The PLL and modulator scheme is designed to support any desired frequency and channel spacing in the range from 240-960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band). Table 11. PLL Synthesizer Block Diagram The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO with integrated on-chip inductors. The output of the VCO is followed by a configurable divider that divides down the signal to the desired output frequency band. The modulus of this divider stage is controlled dynamically by the output from the modulator. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240-960 MHz. 5.6.1. VCO The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0] fields in "Register 75h. Frequency Band Select". In receive mode, the LO frequency is automatically shifted downwards by the IF frequency of 937.5 kHz, allowing receive operation on the same frequency. The VCO integrates the resonator inductor and tuning varactor; so, no external VCO components are required. Rev. 0.5 27 Si4313-B1 The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications, this might not be desirable; so, the VCO calibration may be skipped by setting the appropriate register. 5.7. Crystal Oscillator The Si4313 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 s when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the 30 MHz crystal. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load Capacitance". The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97 fF/step). The crystal shift bit is a coarse shift in frequency but is not binary with xlc[6:0]. The crystal frequency adjustment can be used to compensate for crystal production tolerances. The typical value of the total on-chip capacitance, Cint, can be calculated as follows: C INT = 1.8 pF + 0.085 pF xlc 6:0 + 3.7 pF xtalshift Note that the coarse shift bit crystal shift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning. If AFC is disabled, the synthesizer frequency may be further adjusted by programming the Frequency Offset field fo[9:0]in "Register 73h. Frequency Offset 1" and "Register 74h. Frequency Offset 2", as discussed in "3.5. Frequency Control" on page 22. The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for the entire system, and the BOM cost is reduced. The available clock frequencies and the GPIO configuration are discussed further in "8.2. Microcontroller Clock" on page 33. The Si4313 may also be driven with an external 30 MHz clock signal through the XIN pin. When driving with an external reference or using a TCXO, the crystal load capacitance register should be set to 0. Add R/W Func/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def 7Fh 09 R/W Crystal Oscillator xtalshift Load Capacitance xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 5.8. Regulators There are a total of six regulators integrated onto the Si4313. With the exception of the digital regulator, all regulators are designed to operate with only internal decoupling. The digital regulator requires an external 1 F decoupling capacitor. All regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V. A supply voltage should only be connected to the VDD pins. No voltage should be forced on the digital regulator outputs. 28 Rev. 0.5 Si4313-B1 6. Data Handling 6.1. RX FIFO A 64 byte FIFO is integrated into the chip for RX, as shown below. "Register 7Fh. FIFO Access" is used to access the FIFO. As described in "3.1. Serial Peripheral Interface" on page 17, a burst read from address 7Fh will read data from the RX FIFO. Figure 9. FIFO Threshold The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the incoming RX data reaches the Almost Full Threshold, an interrupt will be generated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. Add R/W Func/ Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def 08 7E R/W R/W Operating & FuncReserved Reserved Reserved tion Control 2 RX FIFO Control Reserved Reserved rxafthr[5] rxmpk rxafthr[4] Reserved rxafthr[3] enldm ffclrrx Reserved 00h rxafthr[0] 37h rxafthr[2] rxafthr[1] The RX FIFO may be cleared or reset with the ffclrrx bit in "Register 08h. Operating Mode and Function Control 2,". All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and "Register 06h. Interrupt Enable 2,". If the interrupts are not enabled, the function will not generate an interrupt on the nIRQ pin, but the bits will still be read correctly in the Interrupt Status registers. Rev. 0.5 29 Si4313-B1 6.2. Preamble Length The preamble detection threshold determines the number of valid preamble bits the radio must receive to qualify a valid preamble. The preamble threshold should be adjusted depending on the nature of the application. The required preamble length threshold will depend on when receive mode is entered in relation to the start of the transmitted packet and the length of the transmit preamble. With a shorter-than-recommended preamble detection threshold, the probability of false detection is directly related to how long the receiver operates on noise before the transmit preamble is received. False detection on noise may cause the actual packet to be missed. The preamble detection threshold is programmed in register 35h. For most applications with a preamble length longer than 32 bits, the default value of 20 is recommended for the preamble detection threshold. A shorter Preamble Detection Threshold Table 12 lists the recommended preamble detection threshold and preamble length for various modes. Table 12. Minimum Receiver Settling Time Approx. Receiver Settling Recommended Preamble Recommended Preamble Time Length with 8-bit Length with 20-bit Detection Threshold Detection Threshold (G)FSK AFC Disabled (G)FSK AFC Enabled OOK 1 byte 2 byte 2 byte 20 bits 28 bits 3 byte 32 bits 40 bits 4 byte *Note: The recommended preamble length and the preamble detection threshold may be shortened when occasional packet errors are tolerable. 6.3. Invalid Preamble Detector When scanning channels in a frequency hopping system it is desirable to determine if a channel is valid in the minimum amount of time. The preamble detector can output an invalid preamble detect signal. which can be used to identify the channel as invalid. After a configurable time set in Register 60h[7:4], an invalid preamble detect signal is asserted indicating an invalid channel. The period for evaluating the signal for invalid preamble is defined as (inv_pre_th[3:0] x 4) x Bit Rate Period. The preamble detect and invalid preamble detect signals are available in "Register 03h. Interrupt/Status 1" and "Register 04h. Interrupt/Status 2." 30 Rev. 0.5 Si4313-B1 7. RX Modem Configuration A Microsoft Excel (WDS) parameter calculator or Wireless Development Suite (WDS) calculator is provided to determine the proper settings for the modem. The calculator can be found on http://www.silabs.com or on the CD provided with the demo kits. An application note is available to describe how to use the calculator and to provide advanced descriptions of the modem settings and calculations via registers 1C-25h. The modulation index is equal to twice the peak deviation divided by the data rate (Rb). Rev. 0.5 31 Si4313-B1 8. Auxiliary Functions 8.1. Smart Reset The Si4313 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector, POR. This reset circuit was designed to produce a reliable reset signal under any circumstances. Reset will be initiated if any of the following conditions occurs: Initial power on, VDD starts from GND: reset is active till VDD reaches VRR (see table). When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR. A software reset via Register 08h. "Operating Mode and Function Control 2," where reset is active for time TSWRST. On the rising edge of a VDD glitch when the supply voltage exceeds the time functioned limit of Figure 10. VDD nom. VDD(t) reset limit: 0.4V+t*0.2V/ms 0.4V actual VDD(t) showing glitch Reset TP t=0, VDD starts to rise reset: Vglitch>=0.4+t*0.2V/ms t Figure 10. POR Glitch Parameters Table 13. POR Parameters Parameter Release Reset Voltage Power-On VDD Slope Low VDD Limit Software Reset Pulse Threshold Voltage Reference Slope VDD Glitch Reset Pulse Symbol VRR SVDD VLD TSWRST VTSD K TP Also occurs after SDN, and initial power on 5 Tested VDD Slope Region VLD 32 Rev. 0.5 Si4313-B1 8.2. Microcontroller Clock The Si4313 can divide its 30 MHz clock down internally, which can then be output to the microcontroller through GPIO2. Additionally, a 32.768 kHz clock signal can also be derived from an internal RC Oscillator or an external 32 kHz Crystal. The GPIO2 default is the microcontroller clock with a 1 MHz microcontroller clock output. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock frequency is selectable from one of eight options listed in Table 14. Table 14. System Clock Frequency Options mclk[2:0] 000 001 010 011 100 101 110 111 Clock Frequency 30 MHz 15 MHz 10 MHz 4 MHz 3 MHz 2 MHz 1 MHz 32.768 kHz Add R/W Func/ Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def 06h 0A R/W Microcontroller Output Clock clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] Except for the 32.768 kHz option, all other frequencies are derived by dividing the Crystal Oscillator frequency. The 32.768 kHz clock signal is derived from an internal RC Oscillator or an external 32 kHz Crystal, depending on which is selected. The GPIO2 default is the microcontroller clock with a 1 MHz microcontroller clock output. If the microcontroller clock option is being used, there may be a need for a system clock for the microcontroller while the Si4313 is in SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in Register 0Ah. Microcontroller Output Clock. When enlfc = 1 and the chip is in SLEEP mode, the 32.768 kHz clock will be provided to the microcontroller as the system clock, regardless of the setting of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin to the microcontroller as the system Clock in all IDLE or RX states. When the chip enters SLEEP mode, the system clock will automatically switch to 32.768 kHz from the RC oscillator or 32.768 crystal. Rev. 0.5 33 Si4313-B1 Another available feature for the microcontroller clock is the clock tail, clkt[1:0] in Register 0Ah. Microcontroller Output Clock. If the low frequency clock feature is not enabled (enlfc = 0), the system clock to the microcontroller is disabled in SLEEP mode. However, it may be useful to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdown of the system clock signal. Setting the clkt[1:0] field will provide additional cycles of the system clock before it shuts off. clkt[1:0] 00 01 10 11 Clock Frequency 0 cycles 128 cycles 256 cycles 512 cycles If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon as the interrupt is read, the state machine will move to the selected mode. For instance, if the chip is commanded to SLEEP mode but an interrupt has occurred, the 30 MHz crystal will be disabled until the interrupt has been cleared. 8.3. Low Battery Detector A low battery detector (LBD) with digital readout is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold". When the digitized battery voltage reaches this threshold, an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller will then confirm the interrupt source by reading "Register 03h. Interrupt/Status 1" and "Register 04h. Interrupt/Status 2." If the LBD is enabled while the chip is in SLEEP mode, it will automatically enable the RC oscillator, which periodically turns on the LBD circuit to measure the battery voltage. The battery voltage may also be read out through "Register 1Bh. Battery Voltage Level" at any time when the LBD is enabled. The low battery detect function is enabled by setting enlbd = 1 in "Register 07h. Operating Mode and Function Control 1". Add R/W Func/ Description Low Battery Detector Threshold Battery Voltage Level 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 POR Def 1A 1B R/W R lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h -- vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled (enlbd = 1 in "Register 07h. Operating Mode and Function Control 1"), the battery voltage may be read at any time by reading "Register 1Bh. Battery Voltage Level". A battery voltage threshold may be programmed in "Register 1Ah. Low Battery Detector Threshold". When the battery voltage level drops below the battery voltage threshold, an interrupt is generated on the nIRQ pin to the microcontroller if the LBD interrupt is enabled in "Register 06h. Interrupt Enable 2". The microcontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03 and 04h. The LSB step size for the LBD ADC is 50 mV, with the ADC range demonstrated in Table 15. If the LBD is enabled, the LBD and ADC will automatically be enabled every 1 s for approximately 250 s to measure the voltage which minimizes the current consumption in Sensor mode. Before an interrupt is activated, four consecutive readings are required. Battery Voltage = 1.7 + 50 mV ADC VALUE 34 Rev. 0.5 Si4313-B1 Table 15. LBD ADC Range ADC Value 0 1 2 -- 29 30 31 VDD Voltage [V] <1.7 1.7-1.75 1.75-1.8 -- 3.1-3.15 3.15-3.2 >3.2 Rev. 0.5 35 Si4313-B1 8.4. Wake-Up Timer and 32 kHz Clock Source The chip contains an integrated wake-up timer which can be used to periodically wake the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will count for a time specified defined in Registers 14-16h, "Wake Up Timer Period." At the expiration of this period an interrupt will be generated on the nIRQ pin if this interrupt is enabled. The microcontroller will then need to verify the interrupt by reading the Registers 03h-04h, "Interrupt Status 1 & 2". The wake-up timer value may be read at any time by the wtv[15:0] read only registers 17h-18h. The formula for calculating the Wake-Up Period is the following: WUT WUT Register wtr[4:0] wtm[15:0] 4 M 2R ms 32 . 768 Description R Value in Formula M Value in Formula Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by using the R value. Add R/W Function/Description 14 15 16 17 18 R/W R/W R/W R R Wake-Up Timer Period 1 Wake-Up Timer Period 2 Wake-Up Timer Period 3 Wake-Up Timer Value 1 Wake-Up Timer Value 2 D7 D6 D5 D4 wtr[4] D3 wtr[3] D2 wtr[2] D1 wtr[1] D0 wtr[0] POR Def. 03h 00h 00h -- -- wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] wtm[7] wtv[15] wtv[7] wtm[6] wtv[14] wtv[6] wtm[5] wtv[13] wtv[5] wtm[4] wtv[12] wtv[4] wtm[3] wtv[11] wtv[3] wtm[2] wtv[10] wtv[2] wtm[1] wtm[0] wtv[9] wtv[1] wtv[8] wtv[0] There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled in "Register 06h. Interrupt Enable 2." If the WUT interrupt is enabled then nIRQ pin will go low when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the microcontroller clock output is available for the microcontroller to use to process the interrupt. The other method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the chip will not change state until commanded by the microcontroller. The different modes of operating the WUT and the current consumption impacts are demonstrated in Figure 11. A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in Register 07h "Operating & Function Control 1", GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set, all internal functions such as WUT, micro-controller clock, and LDC mode will use the 32 kHz XTAL and not the 32 kHz RC oscillator. 36 Rev. 0.5 Si4313-B1 Interrupt Enable enwut =1 ( Reg 06h) WUT Period GPIOX =00001 nIRQ SPI Interrupt Read Chip State Sleep Ready 1.5 mA Sleep Ready 1.5 mA Sleep Ready 1.5 mA Sleep Current Consumption 1 uA 1 uA 1 uA Interrupt Enable enwut =0 ( Reg 06h) WUT Period GPIOX =00001 nIRQ SPI Interrupt Read Chip State Sleep Current Consumption 1 uA Figure 11. WUT Interrupt and WUT Operation Rev. 0.5 37 Si4313-B1 8.5. Low Duty Cycle Mode The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT period. If a valid preamble and sync are detected the receiver on period will be extended for the low duty cycle mode duration (TLDC) to receive all of the packet. The WUT period must be set in conjunction with the low duty cycle mode duration. The R value ("Register 14h. Wake-up Timer Period 1") is shared between the WUT and the TLDC. The ldc[7:0] bits are located in "Register 19h. Low Duty Cycle Mode Duration." The time of the TLDC is determined by the formula below: TLDC ldc [ 7 : 0 ] 42R ms 32 . 768 Figure 12. Low Duty Cycle Mode 38 Rev. 0.5 Si4313-B1 8.6. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW controlAntenna Diversity Switch control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. Note: The ADC should not be selected as an input to the GPIO in standby or sleep modes and will cause excess current consumption. Add R/W Function/Des cription 0B 0C 0D 0E R/W R/W R/W R/W GPIO0 Configuration GPIO1 Configuration GPIO2 Configuration I/O Port Configuration D7 D6 D5 D4 D3 D2 D1 D0 POR Def. gpio0drv[1] gpio0drv[0] gpio1drv[1] gpio1drv[0] gpio2drv[1] gpio2drv[0] extitst[2] pup0 pup1 pup2 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] itsdo dio2 dio1 dio0 00h 00h 00h 00h extitst[1] extitst[0] The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000 default setting. The default settings for each GPIO are listed below: GPIO GPIO0 GPIO1 GPIO2 00000--Default Setting POR POR Inverted Microcontroller Clock For a complete list of the available GPIOs see "AN440: EZRadioPRO Detailed Register Descriptions". The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase the drive strength and current capability of the GPIO by changing the driver size. Special care should be taken in setting the drive strength and loading on GPIO2 when the microcontroller clock is used. Excess loading or inadequate drive may contribute to increased spurious emissions. Rev. 0.5 39 Si4313-B1 8.7. RSSI and Clear Channel Assessment Received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5 dB resolution per bit. Figure 13 demonstrates the relationship between input power level and RSSI value. The absolute value of the RSSI will change slightly depending on the modem settings. The RSSI may be read at anytime, but an incorrect error may rarely occur. The RSSI value may be incorrect if read during the update period. The update period is approximately 10 ns every 4 Tb. For 10 kbps, this would result in a 1 in 40,000 probability that the RSSI may be read incorrectly. This probability is extremely low, but to avoid this, one of the following options is recommended: majority polling, reading the RSSI value within 1 Tb of the RSSI interrupt, or using the RSSI threshold described in the next paragraph for Clear Channel Assessment (CCA). Add R/W 26 27 R R/W Function/Description Received Signal Strength Indicator RSSI Threshold for Clear Channel Indicator D7 rssi[7] rssith[7] D6 rssi[6] rssith[6] D5 rssi[5] rssith[5] D4 rssi[4] rssith[4] D3 rssi[3] rssith[3] D2 rssi[2] rssith[2] D1 rssi[1] rssith[1] D0 rssi[0] rssith[0] POR Def. -- 00h For CCA, threshold is programmed into rssith[7:0] in "Register 27h. RSSI Threshold for Clear Channel Indicator." After the RSSI is evaluated in the preamble, a decision is made if the signal strength on this channel is above or below the threshold. If the signal strength is above the programmed threshold then the RSSI status bit, irssi, in "Register 04h. Interrupt/Status 2" will be set to 1. The RSSI status can also be routed to a GPIO line by configuring the GPIO configuration register to GPIOx[3:0] = 1110. RSSI vs Input Power 250 200 150 RSSI 100 50 0 -120 -100 -80 -60 -40 -20 0 20 In Pow [dBm] Figure 13. RSSI Value vs. Input Power 40 Rev. 0.5 Si4313-B1 9. Reference Design Reference designs, including recommended schematics, BOM, and layouts for many common applications, are available at www.silabs.com. 9'' 4 7=$ 0+] 0&8 & & & & X) Q) S) S) 2SWLRQDO 2SWLRQDO 8 2KP ORDG 5; && 1& *3,2B *3,2B *3,2B 9'5 S) 60$5$ 6'1 ;,1 ;287 1,54 16(/ 6,B5(9% 9'' 9''B5) 1& 1& 5; 1& 6&/. 6', 6'2 9''B',* 1& & (3 & (3 Q) & S) X) 2SWLRQDO 'LUHFW PRGH Figure 14. Reference Test Card 10. Application Notes and Reference Material "AN414: EZRadioPRO Layout Design Guide" "AN415: EZRadioPRO Programming Guide" "AN417: Si4x3x Family Crystal Oscillators" "AN429: Using the DC-DC Converter on the F9xx Series MCU for Single Battery Operation with the EZRadioPRO RF Devices" "AN432: RX BER Measurement on EZRadioPRO with a Looped PN Sequence" "AN439: EZRadioPRO RF Testing QuickStart Guide" "AN440: EZRadioPRO Detailed Register Descriptions" "AN453: Advanced RX BW Calculations and Settings" Rev. 0.5 41 Si4313-B1 11. Customer Support Technical support for the complete family of Silicon Labs wireless products is available by accessing the wireless section of the Silicon Labs' website at www.silabs.com/wireless. For answers to common questions please visit the wireless Knowledge Base at www.silabs.com/support/knowledgebase. 11.1. RX LNA Matching All that is required is a 150 pF coupling capacitor between antenna and RX input. 42 Rev. 0.5 Si4313-B1 12. Register Table and Descriptions Table 16. Register Descriptions Add R/W Function/Desc D7 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R R/W Device Version Device Status Interrupt Status 1 Interrupt Status 2 Interrupt Enable 1 Interrupt Enable 2 Operating & Function Control 1 Operating & Function Control 2 Crystal Oscillator Load Capacitance Microcontroller Output Clock GPIO0 Configuration GPIO1 Configuration GPIO2 Configuration I/O Port Configuration ADC Configuration ADC Sensor Amplifier Offset ADC Value Temperature Sensor Control Temperature Value Offset Wake-Up Timer Period 1 Wake-Up Timer Period 2 Wake-Up Timer Period 3 Wake-Up Timer Value 1 Wake-Up Timer Value 2 Low-Duty Cycle Mode Duration 0 ffovfl ifferr iswdet enfferr enswdet swres antdiv[2] xtalshft Reserved gpio0drv[1] gpio1drv[1] gpio2drv[1] Reserved adcstart/adcdone Reserved adc[7] tsrange[1] tvoffs[7] Reserved wtm[15] wtm[7] wtv[15] wtv[7] ldc[7] Reserved 0 dwn3_bypass afcbd swait_timer[1] Reserved rxosr[7] rxosr[10] ncoff[15] ncoff[7] Reserved crgain[7] rssi[7] rssith[7] D6 0 ffunfl Reserved ipreaval Reserved enpreaval enlbd antdiv[1] xlc[6] Reserved gpio0drv[0] gpio1drv[0] gpio2drv[0] extitst[2] adcsel[2] Reserved adc[6] tsrange[0] tvoffs[6] Reserved wtm[14] wtm[6] wtv[14] wtv[6] ldc[6] Reserved 0 ndec[2] enafc swait_timer[0] Reserved rxosr[6] rxosr[9] ncoff[14] ncoff[6] Reserved crgain[6] rssi[6] rssith[6] D5 0 rxffem Reserved ipreainval Reserved enpreainval enwt antdiv[0] xlc[5] clkt[1] pup0 pup1 pup2 extitst[1] adcsel[1] Reserved adc[5] entsoffs tvoffs[5] Reserved wtm[13] wtm[5] wtv[13] wtv[5] ldc[5] Reserved 0 ndec[1] afcgearh[2] shwait[2] crfast[2] rxosr[5] rxosr[8] ncoff[13] ncoff[5] Reserved crgain[5] rssi[5] rssith[5] Data D4 vc[4] headerr irxffafull irssi enrxffafull enrssi x32ksel rxmpk xlc[4] clkt[0] gpio0[4] gpio1[4] gpio2[4] extitst[0] adcsel[0] Reserved adc[4] entstrim tvoffs[4] wtr[4] wtm[12] wtm[4] wtv[12] wtv[4] ldc[4] lbdt[4] vbat[4] ndec[0] afcgearh[1] shwait[1] crfast[1] rxosr[4] stallctrl ncoff[12] ncoff[4] rxncocomp crgain[4] rssi[4] rssith[4] D3 vc[3] Reserved iext iwut enext enwut Reserved Reserved xlc[3] enlfc gpio0[3] gpio1[3] gpio2[3] itsdo adcref[1] adcoffs[3] adc[3] tstrim[3] tvoffs[3] wtr[3] wtm[11] wtm[3] wtv[11] wtv[3] ldc[3] lbdt[3] vbat[3] filset[3] afcgearh[0] shwait[0] crfast[0] rxosr[3] ncoff[19] ncoff[11] ncoff[3] crgain2x crgain[3] rssi[3] rssith[3] D2 vc[2] Reserved Reserved ilbd Reserved enlbd rxon enldm xlc[2] mclk[2] gpio0[2] gpio1[2] gpio2[2] dio2 adcref[0] adcoffs[2] adc[2] tstrim[2] tvoffs[2] wtr[2] wtm[10] wtm[2] wtv[10] wtv[2] ldc[2] lbdt[2] vbat[2] filset[2] 1p5 bypass anwait[2] crslow[2] rxosr[2] ncoff[18] ncoff[10] ncoff[2] crgain[10] crgain[2] rssi[2] rssith[2] D1 vc[1] cps[1] ipkvalid ichiprdy enpkvalid enchiprdy pllon ffclrrx xlc[1] mclk[1] gpio0[1] gpio1[1] gpio2[1] dio1 adcgain[1] adcoffs[1] adc[1] tstrim[1] tvoffs[1] wtr[1] wtm[9] wtm[1] wtv[9] wtv[1] ldc[1] lbdt[1] vbat[1] filset[1] matap anwait[1] crslow[1] rxosr[1] ncoff[17] ncoff[9] ncoff[1] crgain[9] crgain[1] rssi[1] rssith[1] D0 vc[0] cps[0] icrcerror ipor encrcerror enpor xton Reserved xlc[0] mclk[0] gpio0[0] gpio1[0] gpio2[0] dio0 adcgain[0] adcoffs[0] adc[0] tstrim[0] tvoffs[0] wtr[0] wtm[8] wtm[0] wtv[8] wtv[0] ldc[0] lbdt[0] vbat[0] filset[0] ph0size anwait[0] crslow[0] rxosr[0] ncoff[16] ncoff[8] ncoff[0] crgain[8] crgain[0] rssi[0] rssith[0] POR Default 06h -- -- -- 00h 03h 01h 00h 7Fh 06h 00h 00h 00h 00h 00h 00h -- 20h 00h 03h 00h 01h -- -- 00h 14h -- 01h 40h 0Ah 03h 64h 01h 47h AEh 02h 8Fh -- 1Eh R/W Low Battery Detector Threshold R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Battery Voltage Level IF Filter Bandwidth AFC Loop Gearshift Override AFC Timing Control Clock Recovery Gearshift Override Clock Recovery Oversampling Ratio Clock Recovery Offset 2 Clock Recovery Offset 1 Clock Recovery Offset 0 Clock Recovery Timing Loop Gain 1 Clock Recovery Timing Loop Gain 0 Received Signal Strength Indicator RSSI Threshold for Clear Channel Indicator Rev. 0.5 43 Si4313-B1 Table 16. Register Descriptions (Continued) Add R/W Function/Desc D7 28 29 2A 2B 2C 2D 2E 2F-34 35 36 37 38 39 3A-4E 4F 50-5F 60 61 62 63-68 69 6A-6C 70 71 73 74 75 76 77 78 79 7A 7B 7E 7F R/W R/W RX FIFO Control FIFO Access Reserved fifod[7] Reserved fifod[6] R/W R/W Frequency Hopping Channel Select Frequency Hopping Step Size fhch[7] fhs[7] fhch[6] fhs[6] R/W R/W R/W R/W R/W R/W R/W Modulation Mode Control 1 Modulation Mode Control 2 Frequency Offset 1 Frequency Offset 2 Frequency Band Select Nominal Carrier Frequency 1 Nominal Carrier Frequency 0 Reserved trclk[1] fo[7] Reserved Reserved fc[15] fc[7] Reserved trclk[0] fo[6] Reserved sbsel fc[14] fc[6] R/W AGC Override 1 Reserved sgi R/W Crystal Oscillator/Control Test pwst[2] pwst[1] R/W Channel Filter Coefficient Address Inv_pre_th[3] R/W ADC8 Control Reserved Reserved R/W R/W R/W R/W R/W Preamble Detection Control Sync Word 3 Sync Word 2 Sync Word 1 Sync Word 0 preath[4] sync[31] sync[23] sync[15] sync[7] preath[3] sync[30] sync[22] sync[14] sync[6] R R R/W R R/W R/W R/W Antenna Diversity Register 1 Antenna Diversity Register 2 AFC Limiter AFC Correction Read OOK Counter Value 1 OOK Counter Value 2 Slicer Peak Hold adrssi1[7] adrssib[7] Afclim[7] afc_corr[9] afc_corr[9] ookcnt[7] Reserved D6 adrssia[6] adrssib[6] Afclim[6] afc_corr[8] afc_corr[9] ookcnt[6] attack[2] D5 adrssia[5] adrssib[5] Afclim[5] afc_corr[7] ookfrzen ookcnt[5] attack[1] Reserved preath[2] sync[29] sync[21] sync[13] sync[5] Reserved adc8[5] Reserved Inv_pre_th[2] Inv_pre_th[1] Inv_pre_th[0] Reserved pwst[0] Reserved agcen Reserved txdtrtscale dtmod[1] fo[5] Reserved hbsel fc[13] fc[5] Reserved fhch[5] fhs[5] Reserved rxafthr[5] fifod[5] rxafthr[4] fifod[4] rxafthr[3] fifod[3] rxafthr[2] fifod[2] rxafthr[1] fifod[1] rxafthr[0] fifod[0] 37h -- fhch[4] fhs[4] fhch[3] fhs[3] fhch[2] fhs[2] fhch[1] fhs[1] fhch[0] fhs[0] 00h 00h enphpwdn dtmod[0] fo[4] Reserved fb[4] fc[12] fc[4] manppol eninv fo[3] Reserved fb[3] fc[11] fc[3] enmaninv fd[8] fo[2] Reserved fb[2] fc[10] fc[2] enmanch modtyp[1] fo[1] fo[9] fb[1] fc[9] fc[1] enwhite modtyp[0] fo[0] fo[8] fb[0] fc[8] fc[0] 0Ch 00h 00h 00h 75h BBh 80h lnagain pga3 pga2 pga1 pga0 20h clkhyst enbias2x enamp2x bufovr enbuf 24h chfiladd[3] chfiladd[2] chfiladd[1] chfiladd[0] 00h adc8[4] adc8[3] adc8[2] adc8[1] adc8[0] 10h preath[1] sync[28] sync[20] sync[12] sync[4] preath[0] sync[27] sync[19] sync[11] sync[3] rssi_off[2] sync[26] sync[18] sync[10] sync[2] rssi_off[1] sync[25] sync[17] sync[9] sync[1] rssi_off[0] sync[24] sync[16] sync[8] sync[0] 2Ah 2Dh D4h 00h 00h Data D4 adrssia[4] adrssib[4] Afclim[4] afc_corr[6] peakdeten ookcnt[4] attack[0] D3 adrssia[3] adrssib[3] Afclim[3] afc_corr[5] madeten ookcnt[3] decay[3] D2 adrssia[2] adrssib[2] Afclim[2] afc_corr[4] ookcnt[10] ookcnt[2] decay[2] D1 adrssia[1] adrssib[1] Afclim[1] afc_corr[3] ookcnt[9] ookcnt[1] decay[1] D0 adrssia[0] adrssib[0] Afclim[0] afc_corr[2] ookcnt[8] ookcnt[0] decay[0] POR Default -- -- 00h 00h 18h BCh 26h Note: Detailed register descriptions are available in "AN485: Si4313 Detailed Register Descriptions." 44 Rev. 0.5 Si4313-B1 13. Pin Descriptions: Si4313 XOUT nSEL 15 SCLK 14 SDI 13 SDO 12 VDD_DIG 7 GPIO_0 8 GPIO_1 9 GPIO_2 10 11 NC VDR nIRQ SDN VDD 1 NC 2 NC 3 RX 4 NC 5 6 NC XIN 20 19 18 17 16 GND PAD Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Name VDD_RF TX NC RX NC NC GPIO_0 GPIO_1 GPIO_2 VDR NC VDD_DIG SDO SDI SCLK nSEL nIRQ I/O VDD O -- -- -- O I/O I/O I/O O -- VDD O I I I O Description +1.8 to +3.6 V supply voltage input to all analog +1.7 V regulators. The recommended VDD supply voltage is +3.3 V. Transmit output pin. The PA output is an open-drain connection; so, the L-C match must supply VDD (+3.3 VDC nominal) to this pin. No Connect. No Connect. No Connect. Not connected internally to any circuitry. No Connect General Purpose Digital I/O that may be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for more information. Regulated Output Voltage of the Digital 1.7 V Regulator. A 1 F decoupling capacitor is required. Internally this pin is tied to the paddle of the package. This pin should be left unconnected or connected to GND only. +1.8 to +3.6 V supply voltage input to the Digital +1.7 V Regulator. The recommended VDD supply voltage is +3.3 V. 0-VDD V digital output that provides a serial readback function of the internal control registers. Serial Data input. 0-VDD V digital input. This pin provides the serial data stream for the 4-line serial data bus. Serial Clock input. 0-VDD V digital input. This pin provides the serial data clock function for the 4-line serial data bus. Data is clocked into the Si4313 on positive edge transitions. Serial Interface Select input. 0- VDD V digital input. This pin provides the Select/Enable function for the 4line serial data bus. The signal is also used to signify burst read/write mode. General Microcontroller Interrupt Status output. When the Si4313 exhibits anyone of the Interrupt Events the nIRQ pin will be set low=0. Please see the Control Logic registers section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corresponding SPI Interrupt Status Registers, Address 03h and 04h. No external resistor pull-up is required, but it may be desirable if multiple interrupt lines are connected. Crystal Oscillator Output. Connect to an external 30 MHz crystal or leave floating if driving the Xin pin with an external signal source. Crystal Oscillator Input. Connect to an external 30 MHz crystal or to an external source. If using an external clock source with no crystal, dc coupling with a nominal 0.8 VDC level is recommended with a minimum ac amplitude of 700 mVpp. Shutdown input pin. 0-VDD V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. The exposed metal paddle on the bottom of the Si4313 supplies the RF and circuit ground(s) for the entire chip. It is very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4313. 18 19 XOUT XIN O I 20 PKG SDN PADDLE_GND I GND Rev. 0.5 45 Si4313-B1 14. Ordering Information Part Number SI4313-B1-FM Description ISM Receiver Package Type QFN-20 Pb-free Operating Temperature -40 to 85 C *Note: Add an (R) at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 46 Rev. 0.5 Si4313-B1 15. Package Outline: Si4313-B1 Figure 15 illustrates the package details for the Si4313-B1. Table 17 lists the values for the dimensions shown in the illustration. Figure 15. 20-Pin Quad Flat No-Lead (QFN) Table 17. Package Dimensions Symbol A A1 b D D2 e E E2 L aaa bbb ccc ddd eee Min 0.80 0.00 0.18 2.55 Millimeters Nom 0.85 0.02 0.25 4.00 BSC 2.60 0.50 BSC 4.00 BSC 2.60 0.40 -- -- -- -- -- Max 0.90 0.05 0.30 2.65 2.50 0.30 -- -- -- -- -- 2.70 0.50 0.10 0.10 0.08 0.10 0.10 Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 0.5 47 Si4313-B1 16. Landing Pattern: 20-Pin QFN Figure 16 shows the recommended landing pattern details for the Si4313-B1 in a 20-Pin QFN package. Table 18 lists the values for the dimensions shown in the illustration. Figure 16. 20-Pin QFN Landing Pattern 48 Rev. 0.5 Si4313-B1 Table 18. PCB Land Pattern Dimensions Symbol Min C1 C2 E X1 X2 Y1 Y2 Notes: Millimeters Max 4.00 4.00 0.50 REF 0.20 2.65 0.65 2.65 0.30 2.75 0.75 2.75 3.90 3.90 General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components. Rev. 0.5 49 Si4313-B1 17. Top Marking: 20-Pin QFN Figure 17. Si4313 Top Marking 17.1. Top Mark Explanation Mark Method: Line 1 Marking: Line 2 Marking: YAG Laser X = Part Number R = Die Revision TTTTT = Internal Code Line 3 Marking: YY = Year WW = Workweek 0 = Si4313 B = Revision B1 Internal tracking code. Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. 50 Rev. 0.5 Si4313-B1 NOTES: Rev. 0.5 51 Si4313-B1 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 52 Rev. 0.5 |
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